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74ACQ646 * 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs
January 1990 Revised September 2000
74ACQ646 * 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs
General Description
The ACQ/ACTQ646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental handling functions available are illustrated in Figure 1, Figure 2, Figure 3 and Figure 4. The ACQ/ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Independent registers for A and B busses s Multiplexed real-time and stored data transfers s 300 mil slim dual-in-line package s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT646
Ordering Code:
Order Number 74ACQ646SC 74ACQ464ASPC 74ACTQ646SC 74ACTQ464ASPC Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names A0-A7 B0-B7 CPAB, CPBA SAB, SBA G DIR Descriptions Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation
(c) 2000 Fairchild Semiconductor Corporation
DS010635
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74ACQ646 * 74ACTQ646
Logic Symbols
IEEE/IEC
Function Table
Inputs G H H H L L L L L L L L DIR X X X H H H H L L L L CPAB CPBA H or L H or L X SAB X X X L L H H X X X X SBA X X X X X X X L L H H Output Input Input Input Input Data I/O (Note 1) A0-A7 B0-B7 Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn--Real Time (Transparent Mode) Output Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An--Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An Function

X X X X X
X X X X X
H or L
H or L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition

X
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
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74ACQ646 * 74ACTQ646
Real Time Transfer A-Bus to B-Bus
Real Time Transfer B-Bus to A-Bus
FIGURE 1.
FIGURE 2.
Storage from Bus to Register
Transfer from Register to Bus
FIGURE 3.
FIGURE 4.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) PDIP 140C
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA 50 mA -65C to +150C 300 mA
Recommended Operating Conditions
Supply Voltage (VCC) ACQ ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate V/t ACQ Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate V/t ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
125 mV/ns
DC Electrical Characteristics for ACQ
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) Maximum Input Leakage Current IOLD IOHD ICC (Note 5) IOZT Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Maximum I/O Leakage Current (An, Bn Inputs) VOLP Quiet Output Maximum Dynamic VOL 5.0 1.1 1.5 V 5.5 0.6 6.0 A 5.5 5.5 5.5 5.5 8.0 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.85 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 75 -75 80.0 A mA mA A V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 3) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI(OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Figures 5, 6 (Note 6)(Note 7) V IOUT = 50 A V IOH = -12 mA IOH = -24 mA IOH = -24 mA (Note 3) V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC - 0.1V
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74ACQ646 * 74ACTQ646
DC Electrical Characteristics for ACQ
Symbol VOLV VIHD VILD Parameter Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 Typ -0.6 3.1 1.9
(Continued)
TA = -40C to +85C Guaranteed Limits -1.2 3.5 1.5 V V V Figures 5, 6 (Note 6)(Note 7) (Note 6)(Note 8) (Note 6)(Note 8)
TA = +25C
Units
Conditions
Note 3: Maximum of 8 outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 6: Plastic DIP package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 5V (ACQ). Input-under-test switching 5V to threshold (VILD), 0V to threshold (VIHD) f = 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZT ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum I/O Leakage Current (An, Bn Inputs) Maximum ICC/Input Minimum Dynamic Output Current (Note 10) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 1.1 -0.6 1.7 1.2 8.0 1.5 -1.2 2.0 0.8 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 0.6 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 6.0 1.5 75 -75 80.0 A A mA mA mA A V V V V V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 9) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 9) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Figures 5, 6 (Note 11)(Note 12) Figures 5, 6 (Note 11)(Note 12) (Note 11)(Note 13) (Note 11)(Note 13)
Note 9: All outputs loaded; thresholds on input associated with output under test. Note 10: Maximum test duration 2.0 ms, one output loaded at a time. Note 11: Plastic DIP Package. Note 12: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 13: Max number of data inputs (n) switching. (n - 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD), f = 1 MHz.
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74ACQ646 * 74ACTQ646
AC Electrical Characteristics for ACQ
VCC Symbol tPLH tPHL tPLH tPHL tPLH Parameter Propagation Delay Bus to Bus Propagation Delay Bus to Bus Propagation Delay Clock to Bus Propagation Delay Clock to Bus Propagation Delay SBA or SAB to An or Bn (w/An or Bn HIGH or LOW) tPHL Propagation Delay SBA or SAB to An or Bn (w/An or Bn HIGH or LOW) tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tOS Enable Time G to An or Bn Enable Time G to An or Bn Disable Time G to An or Bn Disable Time G to An or Bn Enable Time DIR to An or Bn Enable Time DIR to An or Bn Disable Time DIR to An or Bn Disable Time DIR to An or Bn Output to Output Skew (Note 15) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 14: Voltage Range 3.3 is 3.3V 0.3V. Voltage Range 5.0 is 5.0V 0.5V Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested.
TA = +25C CL = 50 pF Min 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 2.5 1.5 2.5 1.5 4.5 3.0 4.5 3.0 1.5 1.0 1.5 1.0 Typ 9.0 6.5 9.0 6.5 10.0 7.0 10.0 7.0 9.5 6.5 9.5 6.5 10.5 8.0 10.5 8.0 8.0 5.0 8.0 5.0 11.0 8.5 11.0 8.5 8.0 5.0 8.0 5.0 1.0 0.5 Max 12.0 9.0 12.0 9.0 13.0 9.5 13.0 9.5 12.5 9.0 12.5 9.0 14.5 10.5 14.5 10.5 11.0 7.5 11.0 7.5 15.5 11.0 15.5 11.0 11.0 7.5 11.0 7.5 1.5 1.0
TA = -40C to +85C CL = 50 pF Min 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 2.5 2.5 1.5 2.5 1.5 4.5 3.0 4.5 3.0 1.5 1.0 1.5 1.0 Max 13.0 9.5 13.0 9.5 14.0 10.5 14.0 10.5 13.5 10.0 13.5 10.0 15.5 11.5 15.5 11.5 12.0 8.0 12.0 8.0 17.0 11.5 17.0 11.5 12.0 8.0 12.0 8.0 1.5 1.0 ns ns ns ns ns ns Units
(V) (Note 14) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
ns ns ns ns ns ns ns ns ns
AC Operating Requirements for ACQ
Symbol tS tH tW Parameter Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW
Note 16: Voltage Range 5.0 is 5.0V 0.5V Voltage Range 3.3 is 3.3V 0.3V
VCC (Note 16) 3.3 5.0 3.3 5.0 3.3 5.0
TA = +25C Typ 3.0 3.0 1.5 1.5 4.0 4.0
TA = -40C to +85C Guaranteed Minimum 3.0 3.0 1.5 1.5 4.0 4.0
Units ns ns ns
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74ACQ646 * 74ACTQ646
AC Electrical Characteristics for ACTQ
VCC Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tOSHL tOSLH tOSHL tOSLH Parameter Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An or Bn (w/An or Bn HIGH or LOW) Enable Time G to An or Bn Disable Time G to An or Bn Enable Time DIR to An or Bn Disable Time DIR to An or Bn Output to Output Skew (Note 18) Select to Bus or Clock to Bus Output to Output Skew (Note 18) Bus to Bus
Note 17: Voltage Range 5.0 is 5.0V 0.5V Note 18: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested.
TA = +25C CL = 50 pF Min 2.5 2.0 Typ 8.5 8.0 Max 10.5 10.0
TA = -40C to +85C CL = 50 pF Min 2.5 2.0 Max 11.0 10.5 ns ns Units
(V) (Note 17) 5.0 5.0
5.0
2.5
8.5
10.5
2.5
11.0
ns
5.0 5.0 5.0 5.0
2.5 1.0 2.5 1.0
10.0 7.0 10.0 7.0
12.0 8.5 12.0 8.5
2.5 1.0 2.5 1.0
12.5 9.0 12.5 9.0
ns ns ns ns
5.0
0.5
1.0
1.0
ns
5.0
1.0
1.5
1.5
ns
AC Operating Requirements for ACTQ
VCC Symbol Parameter (V) (Note 19) tS tH tW Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW
Note 19: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 3.0 1.5 4.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 3.0 1.5 4.0 ns ns ns Units
5.0 5.0 5.0
Capacitance
Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Typ 4.5 15.0 90.0 Units pF pF pF VCC = OPEN VCC = 5.0V VCC = 5.0V Conditions
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74ACQ646 * 74ACTQ646
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/VOHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL,until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as V ILD. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 5. Quiet Output Noise Voltage Waveforms
Note 20: VOHV and VOLP are measured with respect to ground reference. Note 21: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 6. Simultaneous Switching Test Circuit
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74ACQ646 * 74ACTQ646
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
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74ACQ646 * 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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